View SN65LVDS302_9045375.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features applications description SN65LVDS302 slls733b ? june 2006 ? revised february 2007 programmable 27-bit serial-to-parallel receiver the serial data and clock are received via sub low-voltage differential signalling (sublvds) lines. serial interface technology the SN65LVDS302 supports three operating power compatible with flatlink?3g such as modes (shutdown, standby, and active) to conserve sn65lvds301 power. supports video interfaces up to 24-bit rgb when receiving, the pll locks to the incoming clock data and 3 control bits received over 1, 2 or clk and generates an internal high-speed clock at 3 sublvds differential lines the line rate of the data lines. the data is serially loaded into a shift register using the internal sublvds differential voltage levels high-speed clock. the deserialized data is presented up to 1.755 gbps data throughput on the parallel output bus with a recreation of the three operating modes to conserve power pixel clock pclk generated from the internal ? active mode qvga - 17 mw high-speed clock. if no input clk signal is present, the output bus is held static with the pclk and de ? typical shutdown - 0.7 m w held low, while all other parallel outputs are pulled ? typical standby mode - 27 m w typical high. bus-swap function for pcb-layout flexibility the parallel (cmos) output bus offers a bus-swap esd rating > 4 kv (hbm) feature. the swap control pin controls the output pixel clock range of 4 mhz?65 mhz pin order of the output pixel data to be either r[7:0]. g[7:0], b[7:0], vs, hs, de or b[0:7], g[0:7], r[0:7], failsafe on all cmos inputs vs, hs, de. this gives a pcb designer the flexibility packaged in 5 mm x 5 mm microstar junior to better match the bus to the lcd driver pinout or to m bga ? with 0,5 mm ball pitch put the receiver device on the top side or the bottom very low emi meets sae j1752/3 'kh'-spec side of the pcb. the f/s control input selects between a slow cmos bus output rise time for best emi and power consumption and a fast cmos output for increased speed or higher load designs. small low-emission interface between graphics controller and lcd display mobile phones & smart phones portable multimedia players the SN65LVDS302 receiver de-serializes flatlink?3g compliant serial input data to 27 parallel data outputs. the SN65LVDS302 receiver contains one shift register to load 30 bits from 1, 2 or 3 serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel cmos outputs after checking the parity bit. if the parity check confirms correct parity, the channel parity error (cpe) output remains low. if a parity error is detected, the cpe output generates a high pulse while the data output bus disregards the newly-received pixel. instead, the last data word is held on the output bus for another clock cycle. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. flatlink is a trademark of texas instruments. m bga is a registered trademark of tessera, inc. production data information is current as of publication date. copyright ? 2006?2007, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www.ti.com flatlink 3g ? 14 7 * 36 9 # 25 8 0 application processor with rgb video interface lvds302 lvds301 lcd driver data clk
description (continued) SN65LVDS302 slls733b ? june 2006 ? revised february 2007 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. two link select lines ls0 and ls1 select whether 1, 2, or 3 serial links are used. the rxen input may be used to put the SN65LVDS302 in a shutdown mode. the SN65LVDS302 enters an active standby mode if the common mode voltage of the clk input becomes shifted to vddlvds (e.g., transmitter releases the clk output into high-impedance). this minimizes power consumption without the need of switching an external control pin. the SN65LVDS302 is characterized for operation over ambient air temperatures of ?40 c to 85 c. all cmos and sublvds signals are 2-v tolerant with vdd=0 v. this feature allows signal powerup before v cc is stabilized. functional block diagram 2 submit documentation feedback www.ti.com 0 1 pll multiplier rxen pclk vs hs b[0:7] g[0:7] r[0:7]de ls1 88 8 sublvds d0+ d0- sublvds d2+ d2- sublvds clk+ clk- sublvds d1+ d1- ls0 cpe rgb=1 hs=vs=1 de=0 1 0 1 0 cpol output buffer swap f/s 27-bit parallel register parity check ipclk ipclk standby or pwr down r bbdc 5050 and glitch suppression v thstby standby control x1 x10, x15, or x30 r bbdc 5050 r bbdc 5050 r bbdc 5050 serial-to-parallel conversion v ddlvds v ddlvds v ddlvds v ddlvds
pinout ? top view SN65LVDS302 slls733b ? june 2006 ? revised february 2007 3 submit documentation feedback www.ti.com 9 8 7 6 4 5 3 2 1 ad c bg f e h j rgb output pin assignment based on swap pin setting: swap = 0 / swap = 1 d 0 - g 0 / g 7 b 7 / r 0 d 2 + d 2 - d 1+ d 1 - d 0 + clk + clk - r 7 / b 0 v ddlvds gnd lvds v ddplld gnd plld gnd plla vdd b 0 / r 7 gnd lvds gnd gnd vdd de gnd gnd gnd hs vs gnd gnd gnd gnd pclk rxen vdd v ddplla gnd b 5 /r 2 vdd b 1 / r 6 vdd gnd b 4 /r 3 vdd b 2 / r 5 b 3 / r 4 gnd gnd gnd gnd gnd gnd gnd gnd cpe gnd b 6 / r 1 swap ls 1 ls 0 cpol gnd vdd r 1 / b 6 g 6 / g 1 g 5 / g 2 g 3 / g 4 g 2 / g 5 g 1 / g 6 r 3 / b 4 r 6 / b 1 r 5 / b 2 r 2 / b 5 r 4 / b 3 g 7 / g 0 r 0 / b 7 g 4 / g 3 f /s v ddlvds gnd lvds pinout - top view
swap pin functionality SN65LVDS302 slls733b ? june 2006 ? revised february 2007 pinout ? top view (continued) the swap pin allows the pcb designer to reverse the rgb bus, minimizing potential signal crossovers due to signal routing. the two drawings beneath show the rgb signal pin assignment based on the swap-pin setting. figure 1. pinout with swap pin = gnd figure 2. pinout with swap pin = vdd 4 submit documentation feedback www.ti.com 9 8 7 6 4 5 3 2 1 ad c bg f e h j g0 b7 r7 b0 de hs vs pclk b5 b1 b4 b2 b3 b6 r1 g6 g5 g3 g2 g1 r3 r6 r5 r2 r4 g7 r0 g4 SN65LVDS302 top view 9 8 7 6 4 5 3 2 1 ad c bg f e h j g7 r0 b0 r7 de hs vs pclk r2 r6 r3 r5 r4 r1 b6 g1 g2 g4 g5 g6 b4 b1 b2 b5 b3 g0 b7 g3 SN65LVDS302 top view
SN65LVDS302 slls733b ? june 2006 ? revised february 2007 pinout ? top view (continued) table 1. pin description pin swap signal pin swap . . signal pin swap signal a1 ? gnd c1 ? ls0 f1 ? d1+ l r6 c2 ? v dd f2 ? v ddplld a2 h b1 c3 unpopulated f3 ? gnd l r4 c4 ? v dd f4 ? gnd a3 h b3 c5 ? gnd f5 ? gnd l r2 c6 ? v dd f6 ? gnd a4 h b5 c7 ? gnd f7 ? v dd l r0 l b7 l b1 a5 c8 f8 h b7 h r0 h r6 l g6 l b6 l b0 a6 c9 f9 h g1 h r1 h r7 l g4 d1 ? d2+ g1 ? d1? a7 h g3 d2 ? ls1 g2 ? gnd lvds l g2 d3 ? gnd g3 ? gnd a8 h g5 d4 ? gnd g4 ? gnd a9 ? gnd d5 ? gnd g5 ? gnd l r7 d6 ? gnd g6 ? gnd b1 h b0 d7 ? v dd g7 ? v dd l r5 l b5 g8 ? f/s b2 d8 h b2 h r2 g9 ? pclk l r3 l b4 h1 ? cpol b3 d9 h b4 h r3 h2 ? v ddlvds l r1 e1 ? d2? h3 ? v ddplla b4 h b6 e2 ? gnd plld h4 ? gnd plla l g7 e3 ? gnd h5 ? v ddlvds b5 h g0 e4 ? gnd h6 ? gnd lvds l g5 e5 ? gnd h7 ? gnd b6 h g2 e6 ? gnd h8 ? vs l g3 e7 ? v dd h9 ? hs b7 h g4 l b3 j1 ? gnd lvds e8 l g1 h r4 j2 ? swap b8 h g6 l b2 j3 ? clk+ e9 l g0 h r5 j4 ? clk? b9 h g7 j5 ? d0+ j6 ? d0? j7 ? rxen j8 ? de j9 ? cpe 5 submit documentation feedback www.ti.com
SN65LVDS302 slls733b ? june 2006 ? revised february 2007 terminal functions name i/o description d0+, d0? sublvds data link (active during normal operation) sublvds data link (active during normal operation when ls0 = high and ls1 = low, or ls0 = low and d1+, d1? ls1=high; high impedance if ls0 = ls1 = low); input can be left open if unused sublvds in sublvds data link (active during normal operation when ls0 = low and ls1 = high, high-impedance d2+, d2? when ls1 = low); input can be left open if unused clk+, clk? sublvds input pixel clock; polarity is fixed. r0?r7 red pixel data (8); pin assignment depends on swap pin setting g0?g7 green pixel data (8); pin assignment depends on swap pin setting b0?b7 blue pixel data (8); pin assignment depends on swap pin setting hs cmos out horizontal sync vs vertical sync de data enable pclk output pixel clock; rising or falling clock polarity is selected by control input cpol ls0, ls1 link select (determines active sublvds data links and pll range) see table 2 disables the cmos drivers and turns off the pll, putting device in shutdown mode 1 ? reciver enabled 0 ? receiver disabled (shutdown) note: rxen input incorporates glitch suppression logic to avoid unwanted switching. the input must be rxen pulled low for longer than 10s continuously to force the receiver to enter shutdown. the input must be pulled high for at least 10 m s continuously to activate the receiver. an input pulse shorter than 5us will be interpreted as glitch and becomes ignored. at power up, the receiver is enabled immediately if rxen=h and disabled if rxen=l output clock polarity selection cmos in cpol 0 ? rising edge clocking 1 ? falling edge clocking bus swap swaps the bus pins to allow device placement on top or bottom of pcb. see pinout drawing for pin assignments. swap 0 ? data output from r7...b0 1 ? data output from b0...r7 cmos bus rise time select f/s 1 ? fast output rise time 0 ? slow output rise time channel parity error this output indicates the detection of a parity error by generating an output high-pulse for half of a pclk clock cycle; this allows counting parity errors with a simple counter. cpe cmos out 0 ? no error high-pulse ? bit error detected v dd supply voltage gnd supply ground v ddlvds sublvds i/o supply voltage gnd lvds sublvds ground power supply v ddplla pll analog supply voltage gnd plla pll analog gnd v ddplld pll digital supply voltage gnd plld pll digital gnd 6 submit documentation feedback www.ti.com
functional description deserialization modes 1-channel mode 2-channel mode SN65LVDS302 slls733b ? june 2006 ? revised february 2007 the SN65LVDS302 receiver has three modes of operation controlled by link-select pins ls0 and ls1. table 2 shows the deserializer modes of operation. table 2. logic table: link select operating modes ls1 ls0 mode of operation data links status 0 0 1chm 1-channel mode (30-bit serialization rate) d0 active; d1, d2 disabled 0 1 2chm 2-channel mode (15-bit serialization rate) d0, d1 active; d2 disabled 1 0 3chm 3-channel mode (10-bit serialization rate) d0, d1, d2 active 1 1 reserved reserved while ls0 and ls1 are held low, the SN65LVDS302 receives payload data over a single sublvds data pair, d0. the pll locks to the sublvds clock input and internally multiplies the clock by a factor of 30. the internal high speed clock is used to shift in the data payload on d0 and to deserialize 30 bits of data. figure 3 illustrates the timing and the mapping of the data payload into the 30-bit frame. the internal high speed clock is divided by a factor of 30 to recreate the pixel clock and the data payload with the pixel clock is presented on the output bus. the reserved bits and parity bit are not output. while in this mode, the pll can lock to a clock that is in the range of 4 mhz through 15 mhz. this mode is intended for smaller video display formats that do not need the full bandwidth capabilities of the SN65LVDS302. figure 3. data and clock input in 1-chm (ls0 and ls1 = low) while ls0 is held high and ls1 is held low, the SN65LVDS302 receives payload data over two sublvds data pairs, d0 and d1. the pll locks to the sublvds clock input and internally multiplies the clock by a factor of 15. the internal high speed clock is used to shift in the data payload on d0 and d1 and to deserialize 15 bits of data from each pair. figure 4 illustrates the timing and the mapping of the data payload into the 30-bit frame. the internal high speed clock is divided by a factor of 15 to recreate the pixel clock, and the data payload with pixel clock is presented on the output bus. the reserved bits and parity bit are not output. while in this mode the pll can lock to a clock that is in the range of 8 mhz through 30 mhz. figure 4. data and clock input in 2-chm (ls0 = high; ls1 = low) 7 submit documentation feedback www.ti.com d0 +/- channel clk + b7 b6 r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 vs hs de res res cp r7 r6 cp res res clk - r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 vs res cp res b7 b6 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 hs de res cp r7 r6 g3 g2 clk + clk - d0 +/- channeld1 +/- channel
3-channel mode powerdown modes shutdown mode standby mode active modes acquire mode (pll approaches lock) SN65LVDS302 slls733b ? june 2006 ? revised february 2007 while ls0 is held low and ls1 is held high the SN65LVDS302 receives payload data over three sublvds data pairs: d0, d1, and d2. the pll locks to the sublvds clock input and internally multiplies the clock by a factor of 10. the internal high speed clock is used to shift in the data payload on d0, d1, and d2, and to deserialize 10 bits of data from each pair. figure 5 illustrates the timing and the mapping of the data payload into the 30-bit frame. while in this mode the pll can lock to a clock that is in the range of 20 mhz through 65 mhz. figure 5. data and clock input in 3-chm (ls0 = low; ls1 = high) the SN65LVDS302 receiver has two powerdown modes to facilitate efficient power management. a low input signal on the rxen pin puts the SN65LVDS302 into shutdown mode. this turns off most of the receiver circuitry including the sublvds receivers, pll, and deserializers. the sublvds differential-input resistance remains 100 w , while any input signal is ignored. all outputs will hold a static output pattern: r[0:7]=g[0:7]=b[0:7]=vs=hs=high; de=pclk=low. the current draw in shutdown mode will be nearly zero if the sublvds inputs are left open or pulled high. the SN65LVDS302 will enter the standby mode when the SN65LVDS302 is not in shutdown mode but the sublvds clock-input common-mode voltage is above 0.9 v ddlvds . the clk input incorporates a pull-up circuit to shift the sublvds clock-input common-mode voltage to v ddlvds in the absence of an input signal. all circuitry except the sublvds clock-input standby monitor is shut down. the SN65LVDS302 will also enter standby mode when the input clock frequency on the clk input is less than 500 khz. the sublvds input resistance remains 100 w while any input signal on the data inputs d0, d1, and d2 becomes ignored. all outputs will hold a static output pattern: r[0:7]=g[0:7]=b[0:7]=vs=hs=high; de=pclk=low. the current drawn in standby mode will be very low. a high input signal on rxen combined with a clk input signal switching faster than 3 mhz and v icm smaller than 1.3 v force the SN65LVDS302 into active mode. current consumption in active mode depends on operating frequency and the number of data transitions in the data payload. clk-input frequencies between 3 mhz and 4 mhz activate the device but proper pll functionality is not secured. it is not recommended to operate the SN65LVDS302 in active mode at clk frequencies below 4 mhz. when the SN65LVDS302 is enabled and a sublvds clock input present, the pll will pursue lock to the input clock. while the pll pursues lock the output data bus will hold a static output pattern: r[0:7]=g[0:7]=b[0:7]=vs=hs=high; de=pclk=low. 8 submit documentation feedback www.ti.com d0 +/- channel clk + b7 b6 r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 vs hs de cp res res cp res res clk - b7 b6 r7 r6 g7 g6 d1 +/- channeld2 +/- channel
receive mode parity error detection and handling SN65LVDS302 slls733b ? june 2006 ? revised february 2007 for proper device operation, the pixel clock frequency must fall within the valid f pclk range specified under recommended operating conditions. if the pixel clock frequency is larger than 3 mhz but smaller than f pclk(min) , the SN65LVDS302 pll is enabled. under such conditions, it is possible for the pll to lock temporarily to the pixel clock, causing the pll monitor to release the device into active receive mode. if this happens, the pll may or may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and pll deadlock (loss of vco oscillation). after the pll achieves lock the device enters the normal receive mode. the output data bus presents the de-serialized data. the pclk output pin outputs the recovered pixel clock. the SN65LVDS302 receiver performs error checking on the basis of a parity bit that is transmitted across the sublvds interface from the transmitting device. once the SN65LVDS302 detects the presence of the clock and the pll has locked onto pclk, then the parity is checked. parity-error detection ensures detection of all single bit errors in one pixel and 50% of all multi-bit errors. the parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus vs, hs, and de. odd parity bit signalling is used. the parity error is output on the cpe pin. if the sum of the 27 data bits and the parity bit result in an odd number, the receive data are assumed to be valid. the cpe output will be held low. if the sum equals an even number, parity error is declared. the cpe output will indicate high for half a pclk period. the cpe output will be set with the data bit transition and cleared after 1/2 the data bit time. this allows counting every detected parity error with a simple counter connected to cpe. 9 submit documentation feedback www.ti.com r[0:7], g[0:7], b[0:7], hs, vs, de pclk (cpol=0) cpe when a parity error is detected, the receiver outputsthe previous pixel on the bus hence no data transitions occur. a parity error is indicated by a high pulse on cpe; the width of the pulse is 1/2 the length of a pclk cycle also if there is a parity error detected then thedata on that pclk cycle is not output. instead, the last valid data from a previous pclk cycle is repeated on the output bus. this is to prevent any bit error that may occur on the lvds link from causing perturbations in vs, hs, or de that may be visually disruptive to a display. the reserved bits are not covered in the parity calculations.
status detect and operating modes flow diagram SN65LVDS302 slls733b ? june 2006 ? revised february 2007 the SN65LVDS302 switches between the power saving and active modes in the following way: table 3. status detect and operating modes descriptions mode characteristics conditions shutdown mode least amount of power consumption (most circuitry turned rxen is set low for longer than 10 m s (1) (2) off); all outputs held static: r[0:7]=g[0:7]=b[0:7]=vs=hs=high de=pclk=low; standby mode low power consumption (standby monitor circuit active; rxen is high for longer than 10 m s, and both clk input pll is shutdown to conserve power); common-mode v icm(clk) above 0.9 v ddlvds , or clk all outputs held static: input floating (2) r[0:7]=g[0:7]=b[0:7]=vs=hs=high de=pclk=low; acquire mode pll pursues lock; all outputs held static: rxen is high; clk input monitor detected clock input r[0:7]=g[0:7]=b[0:7]=vs=hs=high de=pclk=low; common mode and woke up receiver out of standby mode receive mode data transfer (normal operation); rxen is high and pll is locked to incoming clock receiver deserializes data and provides data on parallel output (1) in shutdown mode, all SN65LVDS302 internal switching circuits (e.g., pll, serializer, etc.) are turned off to minimize power consumption. the input stage of any input pin remains active. (2) leaving cmos control inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. all cmos inputs must be tied to a valid logic level v il or v ih during shutdown or standby mode. exceptions are the sublvds inputs clk and dx, which can be left unconnected while not in use. 10 submit documentation feedback www.ti.com power up rxen = 0 rxen low for > 10 s m power up rxen = 1 clk input inactive rxen high for > 10 s m shutdown mode standby mode rxen low for > 10 s m rxen low for > 10 s m receive mode acquire mode v (clk) > 0.9 v or f < 500 khz icm ddlvds clk clk input active v (clk) > 0.9 v icm ddlvds power up rxen = 1 clk active pll achieved lock
SN65LVDS302 slls733b ? june 2006 ? revised february 2007 table 4. operating mode transitions mode transition use case transition specifics shutdown ? standby drive rxen high to enable 1. rxen high > 10 m s receiver 2. receiver enters standby mode a. r[0:7]=g[0:7]=b[0:7]=vs=hs remain high and de=pclk low b. receiver activates clock input monitor standby ? acquire transmitter activity 1. clk input monitor detects clock input activity detected 2. outputs remain static 3. pll circuit is enabled acquire ? receive link is ready to receive 1. pll is active and approaches lock data 2. pll achieves lock within t wakeup 3. d1, d2, and/or d3 become active depending on ls0 and ls1 selection 4. first data word was recovered 5. parallel output bus turns on switching from static output pattern to output first valid data word receive ? standby transmitter requested to 1. receiver disables outputs within t sleep enter standby mode by 2. rx input monitor detects v icm > 0.9 vdd lvds within t sleep input common mode 3. r[0:7]=g[0:7]=b[0:7]=vs=hs transition to high and de=pclk to low on next voltage v icm > 0.9 v ddlvds falling pll clock edge (e.g. transmitter output clock stops or enters 4. pll shuts down. clock activity input monitor remains active high-impedance state) receive/standby ? turn off receiver 1. rxen pulled low for > t pwrdn shutdown 2. r[0:7]=g[0:7]=b[0:7]=vs=hs remain static high or transition to static high and de=pclk remain or transition to static low 3. most ic circuitry is shut down for least power consumption 11 submit documentation feedback www.ti.com
absolute maximum ratings (1) dissipation ratings device power dissipation SN65LVDS302 slls733b ? june 2006 ? revised february 2007 value unit supply voltage range, v dd (2) , v ddplla , v ddplld , v ddlvds ?0.3 to 2.175 v voltage range at any input when vddx > 0 v ?0.5 to 2.175 v or output terminal when vddx 0 v ?0.5 to v dd + 2.175 human body model (3) (all pins) 4 kv electrostatic discharge charged-device mode (4) (all pins) 1500 v machine model (5) (all pins) 200 continuous power dissipation see dissipation rating table ouput current, i o 5 ma (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to the gnd terminals (3) in accordance with jedec standard 22, test method a114-b (4) in accordance with jedec standard 22, test method c101 (5) in accordance with jedec standard 22, test method a115-a circuit derating factor (1) t a = 85 c package t a < 25 c board model above t a = 25 c power rating zqe low-k (2) 592 mw 7.407 mw/ c 148 mw (1) this is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. (2) in accordance with the low-k thermal metric definitions of eia/jesd51-2. parameter test conditions typ max unit f clk at 4 mhz 16.8 v ddx = 1.8 v, t a = 25 c, all outputs terminated with 10 pf mw f clk at 65 mhz 64.7 device power p d dissipation f clk at 4 mhz 27.4 v ddx = 1.95 v, t a = ?40 c, all outputs terminated with 10 pf mw f clk at 65 mhz 128.8 12 submit documentation feedback www.ti.com
recommended operating conditions (1) SN65LVDS302 slls733b ? june 2006 ? revised february 2007 min typ max unit v dd v ddplla supply voltages 1.65 1.8 1.95 v v ddplld v ddlvds test set-up see figure 7 f clk 50mhz; f(noise) = 1hz to 2 ghz 100 supply voltage noise magnitude v ddn(pp) mv 50mhz (all supplies) f clk > 50mhz; f(noise) = 1hz to 1mhz 100 f clk > 50 mhz; f(noise) > 1mhz 40 t a operating free-air temperature ?40 85 c clk+ and clk? 1-channel receive mode, see figure 3 4 15 2-channel receive mode, see figure 4 8 30 mhz f clk input pixel clock frequency 3-channel receive mode, see figure 5 20 65 standby mode (2) , see figure 16 500 khz t dutclk clk input duty cycle 35 65 % d0+, d0?, d1+, d1?, d2+, d2-, clk+, and clk? |v id | magnitude of differential input |v d0+ -v d0- |, |v d1+ -v d1- |, |v d2+ -v d2- |, 70 200 mv voltage |v clk+ -v clk- | during normal operation v icm input voltage common mode range receive or acquire mode 0.6 1.2 v stand-by mode 0.9 v ddlvds d v icm input voltage common mode v icm(n) ? v icm(m) with n=d0, d1, d2, or clk ?100 100 variation between all sublvds and m=d0, d1, d2, or clk mv inputs d v id differential input voltage amplitude v id(n) ? v id(m) with n=d0, d1, d2, or clk ?10 10 variation between all sublvds and m=d0, d1, d2, or clk % inputs t r/f input rise and fall time rxen at vdd; see figure 6-2 800 ps d t r/f input rise or fall time mismatch t r(n) ? t r(m) and t f(n) ? t f(m) with n=d0, d1, ?100 100 ps between all sublvds inputs d2, or clk and m=d0, d1, d2, or clk ls0, ls1, cpol, swap, rxen, f/s v icmosh high-level input voltage 0.7 v dd v dd v v icmosl low-level input voltage 0 0.3 v dd v t inrxen rxen input pulse duration 10 m s r[7:0], g[7:0], b[7:0], vs, hs, pclk, cpe c l output load capacitance 10 pf (1) unused single-ended inputs must be held high or low to prevent them from floating. (2) pclk input frequencies lower than 500 khz force the SN65LVDS302 into standby mode. input frequencies between 500 khz and 3 mhz may or may not activate the SN65LVDS302. input frequencies beyond 3 mhz activate the SN65LVDS302. input frequencies between 500 khz and 4 mhz are not recommended, and can cause pll malfunction. 13 submit documentation feedback www.ti.com
device electrical characteristics SN65LVDS302 slls733b ? june 2006 ? revised february 2007 over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit alternating 1010 test pattern (see table 9 ); all cmos outputs f pclk = 4 mhz 9.8 14.0 terminated with 10 pf; f/s and rxen at v dd ; v ih =v dd , v il =0 v; f pclk = 6 mhz 11.7 15.9 ma v dd =v ddplla =v ddplld =v ddlvds ; f pclk = 15 mhz 19.3 25.0 1chm typical power test pattern (see table 6 ); v id =70 mv, all cmos f pclk = 4 mhz 4.7 outputs terminated with 10 pf; f/s at gnd and rxen at v dd ; f pclk = 6 mhz 6.0 ma v ih =v dd , v il =0 v; v dd =v ddplla =v ddplld =v ddlvds ; f pclk = 15 mhz 13.2 alternating 1010 test pattern (seetable 9 ); all cmos outputs f pclk = 8 mhz 14.3 19.4 terminated with 10 pf; f/s and rxen at v dd ; v ih =v dd , v il =0 v; f pclk = 22 mhz 25.0 33.0 ma v dd =v ddplla =v ddplld =v ddlvds ; f pclk = 30 mhz 26.8 37.0 2chm typical power test pattern (see table 7 ); v id =70 mv, all cmos f pclk = 8 mhz 6.4 outputs terminated with 10 pf; f/s at gnd and rxen at v dd ; rms supply f pclk = 22 mhz 13.7 ma i dd v ih =v dd , v il =0 v; v dd =v ddplla =v ddplld =v ddlvds ; current f pclk = 30 mhz 18.3 alternating 1010 test pattern (see table 9 ); all cmos outputs f pclk = 20 mhz 17.1 27.0 terminated with 10 pf; f/s and rxen at v dd ; v ih =v dd , v il =0 v; ma f pclk = 65 mhz 60.8 68.0 v dd =v ddplla =v ddplld =v ddlvds ; 3chm typical power test pattern (see table 8 ); v id =70 mv, all cmos f pclk = 20 mhz 8.6 outputs terminated with 10 pf; f/s at gnd and rxen at v dd ; ma f pclk = 65 mhz v ih =v dd , v il =0 v; 22.2 v dd =v ddplla =v ddplld =v ddlvds ; standby mode; 15 100 m a rxen=v ih clk and d[0:2] inputs are left open; all control inputs held static high or low; all cmos outputs terminated with 10 pf; shutdown v ih =v dd , v il =0v; v dd =v ddplla =v ddplld =v ddlvds mode; 0.4 10 m a rxen=v il (1) all typical values are at 25 c and with 1.8 v supply unless otherwise noted. 14 submit documentation feedback www.ti.com
input electrical characteristics output electrical characteristics SN65LVDS302 slls733b ? june 2006 ? revised february 2007 over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ (1) max unit d0+, d0?, d1+, d1?, d2+, d2?, clk+, and clk? v thstby input voltage common mode threshold to rxen at v dd 1.3 0.9 v ddlvds switch between receive/acquire mode and v standby mode v thl low-level differential input voltage v d0+ ?v d0? , v d1+ ?v d1? , v d2+ ?v d2? , ?40 mv threshold v clk+ ?v clk- v thh high-level differential input voltage 40 mv threshold i i+ , i i? input leakage current v dd =1.95 v; v i+ = v i? ; 75 m a v i = 0.4 v and v i = 1.5 v i ioff power-off input current v dd =gnd; v i = 1.5v ?75 m a r id differential input termination resistor value 78 100 122 w c in input capacitance measured between input terminal 1 pf and gnd d c in input capacitance variation within one signal pair 0.2 pf between all signals 1 r bbdc pull-up resistor for standby detection 21 30 39 k w ls0, ls1, cpol, swap, rxen, f/s v ik input clamp voltage i i = ?18 ma, v dd =v dd (min) -1.2 v i icmos input current (2) 0 v v dd 1.95 v; v i =gnd or 100 na v i =1.95 v c in input capacitance 2 pf i ih high-level input current v in = 0.7 v dd -200 200 na i il low-level input current v in = 0.3 v dd ?200 200 v ih high-level input voltage 0.7 v dd v dd v v il low-level input voltage 0 0.3 v dd (1) all typical values are at 25 c and with 1.8 v supply unless otherwise noted. (2) do not leave any cmos input unconnected or floating to minimize leakage currents. every input must be connected to a valid logic level v ih or v ol while power is supplied to v dd . over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit r[0:7], g[0:7], b[0:7], vs, hs, pclk, cpe 1-chm, f/s=l, i oh =?250 m a 2-or 3-chm, f/s=l, i oh =?500 m a v oh high-level output current 0.8 v dd v dd v 1-chm, f/s=h, i oh =?500 m a 2- or 3-chm, f/s=h, i oh =?2.0 ma 1-chm, f/s=l, i ol =250 m a 2- or 3-chm, f/s=l, i ol =500 m a v ol low-level output current 0 0.2 v dd v 1-chm, f/s=h, i ol =500 m a 2- or 3-chm, f/s=h, i ol =2.0 ma i oh high-level output current 1-chm, f/s=l ?250 2- or 3-chm, f/s=l; 1-chm, f/s=h ?500 2- or 3-chm, f/s=h ?2000 m a i ol low-level output current 1-chm, f/s=l 250 2- or 3-chm, f/s=l; 1-chm, f/s=h 500 2- or 3-chm, f/s=h 2000 15 submit documentation feedback www.ti.com
switching characteristics SN65LVDS302 slls733b ? june 2006 ? revised february 2007 over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit d0+, d0?, d1+, d1?, d2+, d2?, clk+, and clk? t r/f input rise and fall time rxen at v dd ; see figure 6-2 800 ps d t r/f input rise or fall time t r (n)? t r (m) and t f (n)- t f (m) with n=d0, d1, d2, or clk ?100 100 mismatch between all and m=d0, d1, d2, or clk ps sublvds inputs r[7:0], g[7:0], b[7:0], vs, hs, pclk, cpe 1-channel mode, f/s=l 8 16 2-channel mode, f/s=l 4 8 3-channel mode, f/s=l 4 8 rise and fall time 20%? t r/f c l = 10 pf (3) ; see figure 9 ns 80% of v dd (2) 1-channel mode, f/s=h 4 8 2-channel mode, f/s=h 1 2 3-channel mode, f/s=h 1 2 1-channel and 3-channel mode 45% 50% 55% t outp pclk output duty cycle cpol=v il , 2-channel mode 48% 53% 59% cpol=v ih , 2-channel mode 41% 47% 52% output skew between pclk see figure 9 t osk and r[0:7], g[0:7], b0:7], ?500 500 ps hs, vs, and de input to output response time t pd(l) propagation delay time from rxen at v dd , v ih =v dd , v il =gnd, c l =10 pf, see 1.4/f pclk 1.9/f pclk 2.5/f pclk s clk+ input to pclk output figure 14 t gs rxen glitch suppression v ih =v dd , v il =gnd, rxen toggles between v il and v ih ; 3.8 m s pulse width (4) see figure 15 and figure 16 t pwrup enable time from power time from rxen pulled high to data outputs enabled and 2 ms down ( - rxen) outputs valid data; see figure 16 t pwrdn disable time from active rxen is pulled low during receive mode; time mode ( rxen) measurement until all outputs held static: 11 m s r[0:7]=g[0:7]=b[0:7]=vs=hs=high, de=pclk=low and pll is shutdown; see figure 16 rxen at v dd ; device is in standby; time measurement enable time from standby t wakeup from clk input starts switching to pclk and data 2 ms ( - clk) outputs enabled and outputting valid data; see figure 17 rxen at v dd ; device is receiving data; time measurement from clk input signal stops (input open or disable time from active input common mode vicm exceeds threshold voltage t sleep mode (clk transitions to v thstby ) until all outputs held static: 3 m s high-impedance) r[0:7]=g[0:7]=b[0:7]=vs=hs=high, de=pclk=low and pll is shutdown; see figure 17 2-chm; f pclk =22mhz 0.087 fp clk tested from clk input to f bw pll bandwidth (5) mhz pclk output 3-chm; f pclk =65mhz 0.075 fp clk (1) all typical values are at 25 c and with 1.8 v supply unless otherwise noted. (2) t r/f depends on the f/s setting and the capacitive load connected to each output. some application information of how to calculate t r/f based on the output load and how to estimate the timing budget to interconnect to an lcd driver are provided in the application section near the end of this data sheet. (3) the output rise and fall time is optimized for an output load of 10 pf. the rise and fall time can be adjusted by changing the output load capacitance. (4) the rxen input incorporates a glitch-suppression logic to disregard short input pulses. t gs is the duration of either a high-to-low or low-to-high transition that is suppressed. (5) when using the SN65LVDS302 receiver in conjunction with the sn65lvds301 transmitter in one link, the pll bandwidth of the SN65LVDS302 receiver always exceed the bandwidth of the sn65lvds301 transmit pll. this ensures stable pll tracking under all operating conditions and maximizes the receiver skew margin. 16 submit documentation feedback www.ti.com
timing characteristics SN65LVDS302 slls733b ? june 2006 ? revised february 2007 figure 6. SN65LVDS302 pll bandwidth (also showing the sn65lvds301 pll bandwidth) parameter test conditions min max unit 1chm: x=0..29, f pclk =15 mhz; f clk =15 mhz (4) 630 rxen at v dd , v ih =v dd , f clk =4 mhz to 15 mhz (5) v il =gnd, r l =100 w , test setup as in figure 8 , test pattern as in table 11 2chm: x = 0..14, f clk =30 mhz (4) 630 f pclk =30 mhz receiver input skew f clk =8 mhz to 30 mhz (5) t rskmx rxen at v dd , v ih =v dd , margin; see (3) and ps (1) (2) v il =gnd, r l =100 w , test setup figure 43 as in figure 8 , test pattern as in table 12 3chm: f clk = 65 mhz (4) 360 rxen at v dd , v ih =v dd , f clk = 20 mhz to 65 v il =gnd, test setup as in mhz (5) figure 8 , test pattern as in table 13 (1) receiver input skew margin (t rskm ) is the timing margin available for transmitter output pulse position (t ppos ), interconnect skew, and interconnect inter-symbol interference. trskm represents the reminder of the serial bit time not taken up by the receiver strobe uncertainty;. the t rskm assumes a bit error rate better than 10 -12 . (2) t rskm is indirectly proportional to the internal set-up and hold time uncertainty, isi and duty cycle distortion from the front end receiver, the skew missmatch between clk and data d0, d1, and d2, as well as the pll cycle-to-cycle jitter. (3) this includes the receiver internal set-up and hold time uncertainty, all pll related high-frequency random and deterministic jitter components that impact the jitter budget, isi and duty cycle distortion from the front end receiver, and the skew between clk and data d0, d1, and d2; the pulse position min/max variation is given with a bit error rate target of 10 ?12 ; measurements of the total jitter are taken over a sample amount of > 10 ?12 samples. (4) the minimum and maximum limits are based on statistical analysis of the device performance over process, voltage, and temp ranges. (5) these minimum and maximum limits are simulated only. 17 submit documentation feedback www.ti.com 4 mhz 9 % 8 mhz 9 % 20 mhz 8.7 % 15 mhz 8.1 % 30 mhz 8.1 % spec limit 1 chm spec limit 2 chm spec limit 3 chm 65 mhz 7.5 % 9.08.5 7.5 7.0 6.5 8.06.0 0 10 20 30 40 50 60 70 pclk - frequency - mhz pll - bandwidth - % 12 11 10 98 7 6 5 4 pll bw (% of pclk frequency) pll - frequency - mhz 100 0 200 300 400 600 500 700 ps 480 f 30 2 1 clk - ps 480 f 15 2 1 clk - ps 410 f 10 2 1 clk -
parameter measurement information SN65LVDS302 slls733b ? june 2006 ? revised february 2007 figure 7. power supply noise test set-up figure 8. jitter budget 18 submit documentation feedback www.ti.com note : the generator regulates the noise amplitude at point to thetarget amplitude given under the table recommended operating conditions 1. 6 h noise generator 100 mv SN65LVDS302 v ddplla 10 f 1.8 v supply 1 2 1 1 w v ddplld v dd v ddlvds gnd t rskm (p) ideal receiver strobe position c t pg_error t rskm (n) t rskm - is the smaller of the two measured values t rskm (p) and t rskm (n) t pg_error - test equipment (pattern generator) intrinsic output pulse position timing uncertainty t bit - serial bit time c - lvds302 set-up and hold-time uncertainty note: c can be derived by subtracting the receiver skew margin t rskm (p) + t rskm (p) from one serial bit time clk and data pattern generator clk d1 d2 d3 dut: SN65LVDS302 bit error detector t bit to measure t rskm, clk is advanced or delayed with respect to data until errors are observed at the receiver outputs. the advance or delay is then reduced until there are no data errors observed over 10 -12 serial bit times. the magnitude of the advance or delay is t rskm programmable delay
SN65LVDS302 slls733b ? june 2006 ? revised february 2007 parameter measurement information (continued) figure 9. output rise/fall, setup/hold time figure 10. sublvds differential input rise and fall time defintion figure 11. equivalent input circuit design 19 submit documentation feedback www.ti.com t setup t hold 20% (v oh -v ol ) r[7:0], g[7:0], b[7:0], hs, vs, de pclk (cpol=0) t osk t f t r t f t r v oh v ol 80% (v oh -v ol ) 50% (v oh - Cv ol ) 20% (v oh -v ol ) 80% (v oh -v ol ) note: the set-up and hold-time of cmos outputs r[7:0], g[7:0], b[7:0], hs, vs, and de in relation to pclk can be calulated by: t = s&h 1 2 - r pclk -t - t - t ref osk dutp d t r 0 v v C v , v C v dx+ dxC clk+ clkC 80%(v ) id 100%(v ) ic t f 20%(v ) id 0%(v ) id gainstage r id /2 r id /2 r bbdc standby detection line end termination esd clkC, dxC clk+, dx+ v ddlvds
SN65LVDS302 slls733b ? june 2006 ? revised february 2007 parameter measurement information (continued) figure 12. i/o voltage and current definition figure 13. cmos output test circuit, signal and timing definition 20 submit documentation feedback www.ti.com sublvds input cmos output rgb, vs, hs,cpe pclk i o clk-, dx- clk+, dx+ i i+ i i- v o v i- v i+ v id (v i+ +v i- )/2 v icm cmos input swap, cpol, lsx, rxen, f/s i icmos v icmos SN65LVDS302 c =10 pf l rgb, vs, hs, cpe, pclk v o
SN65LVDS302 slls733b ? june 2006 ? revised february 2007 parameter measurement information (continued) figure 14. propagation delay input to output (ls0=ls1=0) figure 15. receiver phase lock loop set time and receiver enable time 21 submit documentation feedback www.ti.com t pd(l) cp r7 r7 r6 r5 r4 cp pixel (nC1) pixel (n) r7 r7 (nC3) r7 (nC1) r6 (nC3) r6 (nC1) v dd/2 pclk (cpol = 0) d0+ clk+ clkC cmos data out r7r6 r7 (nC2) r7 (nC1) r7 (n) r7 (n+1) pixel (n+1) pixel (nC1) rxen clk vco internal signal v dd /2 t gs t pll t pwrup pclk r[7:0], g[7:0], b[7:0], vs, hs pll approaches lock de
power consumption tests SN65LVDS302 slls733b ? june 2006 ? revised february 2007 parameter measurement information (continued) figure 16. receiver enable/disable glitch suppression time figure 17. standby detection table 5 shows an example test pattern word. table 5. example test pattern word word r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x7c3e1e7 7 c 3 e 1 e 7 r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 g3 g2 g1 g0 b7 b6 b5 b4 b3 b2 b1 b0 0 vs hs de 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 22 submit documentation feedback www.ti.com receiver disabled (off) receiver enabled (on) receiver aquires lock rx turns off t gs < 20 ns rxen glitch shorterthan t gs will be ignored pclk less than 20ns spike will be rejected glitch shorterthan t gs will be ignored i cc t pwrup t gs t pwrdn clk rx disabled (off) 2 s m 3 s m t sleep receiver disabled (off) rx enabled output data valid receiver aquires lock, outputs still disabled pclk t wakeup clk rx disabled (off) rx enabled; output data invalid r[7:0], g[7:0], b[7:0], vs, hs,
typical ic power consumption test pattern SN65LVDS302 slls733b ? june 2006 ? revised february 2007 typical power-consumption test patterns consist of sixteen 30-bit receive words in 1-channel mode, eight 30-bit receive words in 2-channel mode and five 30-bit receive words in 3-channel mode. the pattern repeats itself throughout the entire measurement. it is assumed that every possible code on the rgb outputs has the same probability to occur during typical device operation. table 6. typical ic power consumption test pattern, 1-channel mode word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x0000007 2 0xfff0007 3 0x01fff47 4 0xf0e07f7 5 0x7c3e1e7 6 0xe707c37 7 0xe1ce6c7 8 0xf1b9237 9 0x91bb347 10 0xd4ccc67 11 0xad53377 12 0xacb2207 13 0xaab2697 14 0x5556957 15 0xaaaaab3 16 0xaaaaaa5 table 7. typical ic power consumption test pattern, 2-channel mode word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x0000001 2 0x03f03f1 3 0xbffbff1 4 0x1d71d71 5 0x4c74c71 6 0xc45c451 7 0xa3aa3a5 8 0x5555553 table 8. typical ic power consumption test pattern, 3-channel mode word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0xffffff1 2 0x0000001 3 0xf0f0f01 4 0xcccccc1 5 0xaaaaaa7 23 submit documentation feedback www.ti.com
maximum power consumption test pattern output skew pulse position and jitter performance SN65LVDS302 slls733b ? june 2006 ? revised february 2007 the maximum (or worst-case) power consumption of the SN65LVDS302 is tested using the two different test pattern shown in table. test patterns consist of sixteen 30-bit receive words in 1-channel mode, eight 30-bit receive words in 2-channel mode, and five 30-bit receive words in 3-channel mode. the pattern repeats itself throughout the entire measurement. it is assumed that every possible code on rgb outputs has the same probability to occur during typical device operation. table 9. worst-case power consumption test pattern word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0xaaaaaa5 2 0x5555555 table 10. worst-case power consumption test pattern word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x0000000 2 0xffffff7 the following test patterns are used to measure the output skew pulse position and the jitter performance of the SN65LVDS302. the jitter test pattern stresses the interconnect, particularly to test for isi, using very long run-lengths of consecutive bits, and incorporating very high and low data rates, maximizing switching noise. each pattern is self-repeating for the duration of the test. table 11. receive jitter test pattern, 1-channel mode word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x0000001 2 0x0000031 3 0x00000f1 4 0x00003f1 5 0x0000ff1 6 0x0003ff1 7 0x000fff1 8 0x0f0f0f1 9 0x0c30c31 10 0x0842111 11 0x1c71c71 12 0x18c6311 13 0x1111111 14 0x3333331 15 0x2452413 16 0x22a2a25 17 0x5555553 18 0xdb6db65 19 0xcccccc1 20 0xeeeeee1 21 0xe739ce1 22 0xe38e381 24 submit documentation feedback www.ti.com
SN65LVDS302 slls733b ? june 2006 ? revised february 2007 table 11. receive jitter test pattern, 1-channel mode (continued) word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 23 0xf7bdee1 24 0xf3cf3c1 25 0xf0f0f01 26 0xfff0001 27 0xfffc001 28 0xffff001 29 0xffffc01 30 0xfffff01 31 0xfffffc1 32 0xffffff1 25 submit documentation feedback www.ti.com
SN65LVDS302 slls733b ? june 2006 ? revised february 2007 table 12. receive jitter test pattern, 2-channel mode word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x0000001 2 0x000fff3 3 0x8008001 4 0x0030037 5 0xe00e001 6 0x00ff001 7 0x007e001 8 0x003c001 9 0x0018001 10 0x1c7e381 11 0x3333331 12 0x555aaa5 13 0x6dbdb61 14 0x7777771 15 0x555aaa3 16 0xaaaaaa5 17 0x5555553 18 0xaaa5555 19 0x8888881 20 0x9242491 21 0xaaa5571 22 0xcccccc1 23 0xe3e1c71 24 0xffe7ff1 25 0xffc3ff1 26 0xff81ff1 27 0xfe00ff1 28 0x1ff1ff1 29 0xffcffc3 30 0x7ff7ff1 31 0xfff0007 32 0xffffff1 table 13. receive jitter test pattern, 3-channel mode word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 1 0x0000001 2 0x0000001 3 0x0000003 4 0x0101013 5 0x0303033 6 0x0707073 7 0x1818183 8 0xe7e7e71 9 0x3535351 10 0x0202021 11 0x5454543 26 submit documentation feedback www.ti.com
SN65LVDS302 slls733b ? june 2006 ? revised february 2007 table 13. receive jitter test pattern, 3-channel mode (continued) word test pattern: r[7:4], r[3:0], g[7:4], g[3:0], b[7-4], b[3-0], 0,vs,hs,de 12 0xa5a5a51 13 0xadadad1 14 0x5555551 15 0xa6a2aa3 16 0xa6a2aa5 17 0x5555553 18 0x5555555 19 0xaaaaaa1 20 0x5252521 21 0x5a5a5a1 22 0xababab1 23 0xfdfcfd1 24 0xcaaaca1 25 0x1818181 26 0xe7e7e71 27 0xf8f8f81 28 0xfcfcfc1 29 0xfefefe1 30 0xffffff1 31 0xffffff5 32 0xffffff5 27 submit documentation feedback www.ti.com
typical characteristic curves SN65LVDS302 slls733b ? june 2006 ? revised february 2007 some of the plots in this section show more than one curve representing various device pin relationships. taken together, they represent a working range for the tested parameter. supply current vs temperature quiescent supply current vs temperature figure 18. figure 19. supply current vs frequency, 1-channel mode supply current vs frequency, 2-channel mode figure 20. figure 21. supply current vs frequency, 3-channel mode receiver strobe position vs temperature figure 22. figure 23. 28 submit documentation feedback www.ti.com -50 -30 -10 10 30 50 70 90 temperature - c iddq - a m 0.1 1.0 10.0 100.0 powerdown standby 0 20 25 30 -50 -30 -10 10 30 50 70 90 temperature - c idd - ma 5 10 15 2-channel mode, 11 mhz (hvga), f/s = 0 2-channel mode, 22 mhz (vga), f/s = 1 2-channel mode, 11 mhz (hvga), f/s = 1 2-channel mode, 22 mhz (vga), f/s = 0 0 5 10 15 20 25 30 35 40 0 5 10 15 20 f - frequency - mhz 1 - chm, f/s = 0, typ pwr i - ma dd 1 - chm f/s = 0, jitter test 1 - chm, f/s = 1, jitter test 1 - chm, f/s = 1, typ pwr 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 f - frequency - mhz 2 - chm f/s = 0, jitter test 2 - chm, f/s = 1, jitter test i - ma dd 2 - chm, f/s = 1, typ pwr 2 - chm, f/s = 0, typ pwr 0 5 10 15 20 25 30 35 40 15 20 25 30 35 40 45 50 55 60 f - frequency - mhz 3 - chm f/s = 0, jitter test 3 - chm, f/s = 1, jitter test 3 - chm, f/s = 0, typ pwr i - ma dd 3 - chm, f/s = 1, typ pwr 0 50 100 150 200 250 300 350 400 450 -40 -20 0 20 40 60 80 temperature - c 1-chm 11 mhz (hvga) 2-chm 22 mhz (vvga) 3-chm 56 mhz (xga) fl3g limit limit with rskm=130 ps t(rspos) 3-chm 65 mhz
SN65LVDS302 slls733b ? june 2006 ? revised february 2007 typical characteristic curves (continued) pll bandwidth pclk cycle-to-cycle output jitter figure 24. figure 25. rskm, 1-channel mode vs bit rate figure 26. 29 submit documentation feedback www.ti.com 2-chm 2-chm 3-chm 3-chm 3-chm 3-chm spec limit 3chm spec limit 2chm 8 mhz: 9% spec limits1-ch mode 0.0 2.0 4.0 6.0 8.0 10.0 12.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 spec limits2-ch mode spec limits3-ch mode pll bandwidth - % frequency - mhz 0 100 200 300 400 500 600 700 800 900 0 10 frequency - mhz 20 30 40 50 60 70 cc jitter - ps 1-chm 2-chm 3-chm 120 170 220 270 320 370 420 dr - mbps bit width trskm 1chm trskm - tppos 225ps receiver strobe position uncertainty -2000 -1500 -1000 -500 0 500 1000 1500 2000 225 - -225 t(ppos ) minimum desired interconnect budget additional interconnect margin rskm - ps
SN65LVDS302 slls733b ? june 2006 ? revised february 2007 typical characteristic curves (continued) rskm, 2-channel mode vs bit rate rskm, 3-channel mode vs bit rate figure 27. figure 28. qvga output waveform vga 2-channel output waveform figure 29. figure 30. vga 2-channel output waveform vga3-channel output waveform figure 31. figure 32. 30 submit documentation feedback www.ti.com 120 170 220 270 320 370 420 -2000 -1500 -1000 -500 0 500 1000 1500 2000 dr - mbps time - ps 225 ps 225 ps bit width trskm trskm - tppos trskm - tppos trskm bit width -2000 -1500 -1000 -500 0 500 1000 1500 2000 200 250 300 350 400 450 500 550 600 650 225 ps 225 ps dr - mbps time - ps bit width trskm trskm - tppos trskm - tppos trskm bit width C251 C190 0 190 249 response over 80-inch of fr-4 + 1m coax cable 1 ns/div 1-channel mode, f(pclk) = 5.5 mhz output voltage amplitude - mv C250 C190 0 190 250 response over 8-inch fr-4 + 1m coax cable 500 ps/div 2-channel mode, f(pclk) = 22 mhz output voltage amplitude - mv C251 C190 0 190 249 response over 80-inch fr-4 + 1m coax cable 500 ps/div 2-channel mode, f(pclk) = 22 mhz output voltage amplitude - mv C251 C190 0 190 249 output voltage amplitude - mv response over 80-inch fr-4 + 1m coax cable 1 ns/div 3-channel mode, f(pclk) = 22 mhz
SN65LVDS302 slls733b ? june 2006 ? revised february 2007 typical characteristic curves (continued) xga 3-channel output waveform xga 3-channel output waveform figure 33. figure 34. input common-mode noise rejection vs frequency input return loss figure 35. figure 36. input differential crosstalk vs frequency phase noise figure 37. figure 38. 31 submit documentation feedback www.ti.com C251 C190 0 190 249 output voltage amplitude - mv response over 80-inch fr-4 + 1m coax cable 300 ps/div 3-channel mode, f(pclk) = 56 mhz output voltage amplitude - mv 400 mv/div response with 10-pf load 3.5 ns/div 3-channel mode, f(pclk) = 56 mhz 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency - mhz cmnr - db -20.0 -18.0 -16.0 -14.0 -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency - mhz differential s11 - db f(pclk) = 65 mhz -50-60 -70 -80 -90 -100 -110 -120-130 -140 -150 -160 -170 -180 1 10 100 1k 10k 100k 1m 10m dbc/hz frequency - hz -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 frequency - mhz differential xtalk - db
SN65LVDS302 slls733b ? june 2006 ? revised february 2007 typical characteristic curves (continued) gtem sae j1752/3 emi test figure 39. 32 submit documentation feedback www.ti.com frequency - mhz radiated emission - db v m 0 5 10 15 20 25 30 0 200 400 600 800 1000 1200 1400 1600 1800 2000 f(pclk)=62 mhz
application information preventing increased leakage currents in control inputs power supply design recommendation SN65LVDS302 decoupling recommendation vga application SN65LVDS302 slls733b ? june 2006 ? revised february 2007 a floating (left open) cmos input allows leakage currents to flow from v dd to gnd. do not leave any cmos input unconnected or floating. every input must be connected to a valid logic level v ih or v ol while power is supplied to v dd . this also minimizes the power consumption of standby and power down mode. for a multilayer pcb, it is recommended to keep one common gnd layer underneath the device and connect all ground terminals directly to this plane. the SN65LVDS302 was designed to operate reliably in a constricted environment with other digital switching ics. in cell phone designs, the SN65LVDS302 often shares a power supply with various other ics. the SN65LVDS302 can operate with power supply noise as specified in recommend device operating conditions. to minimize the power supply noise floor, provide good decoupling near the SN65LVDS302 power pins. the use of four ceramic capacitors (two 0.01 m f and two 0.1 m f) provides good performance. at the very least, it is recommended to install one 0.1 m f and one 0.01 m f capacitor near the SN65LVDS302. to avoid large current loops and trace inductance, the trace length between decoupling capacitor and ic power inputs pins must be minimized. placing the capacitor underneath the SN65LVDS302 on the bottom of the pcb is often a good choice. figure 40 shows a possible implementation of a standard 640x480 vga display. the lvds301 interfaces to the SN65LVDS302, which is the corresponding receiver device to deserialize the data and drive the display driver. the pixel clock rate of 22 mhz assumes ~10% blanking overhead and 60 hz display refresh rate. the application assumes 24-bit color resolution. also shown is how the application processor provides a powerdown (reset) signal for both serializer and the display driver. the signal count over the flexible printed circuit board (fpc) could be further decreased by using the standby option on the SN65LVDS302 and pulling rxen high with a 30 k w resistor to v dd . figure 40. typical vga display application 33 submit documentation feedback www.ti.com spi reset 22mhz 27 pclk r[7:0] g[7:0] b[7:0] hs,vs,de d[7:0] d[15:8] d[23:16] hs,vs,de pixel clk vddx gnd 2x0.01uf 2x0.1uf ls0 ls1 txen 1.8v vddx gnd 2x0.01uf 2x0.1uf ls0 ls1 rxen 1.8v d0+ d0- clk+ clk- d1+ d1- d0+ d0- clk+ clk- d1+ d1- gnd 1.8v 2.7v gnd 1.8v 2.7 v gnd gnd lcd with vga resolution 22mhz 27 pclk r[7:0] g[7:0] b[7:0] hs,vs,de spi serial port interface (3-wire if) 3 application processor (e.g. omap) sn65lvds301 sn65lvds 302 video mode display driver fpc 22mhz 330mbps 330mbps enable if fpc wire count is critical , replace this connection with a pull - up resistor at rxen
dual lcd-display application typical application frequencies SN65LVDS302 slls733b ? june 2006 ? revised february 2007 application information (continued) the example in figure 41 shows a possible application setup driving two video-mode displays from one application processor. the data rate of 330 mbps at a pixel clock rate of 5.5 mhz corresponds to a 320x240 qvga resolution at 60 hz refresh rate and 10% blanking overhead. figure 41. example dual-qvga display application the SN65LVDS302 supports pixel clock frequencies from 4 mhz to 65 mhz over 1, 2, or 3 data lanes. table 14 provides a few typical display resolution examples and shows the number of data lanes necessary to connect the SN65LVDS302 with the display. the blanking overhead is assumed to be 20%. often, blanking overhead is smaller, resulting in a lower data rate. furthermore, the examples in the table assumes a display frame refresh rate of 60-hz. the actual refresh rate may differ depending on the application-processor clock implementation. table 14. typical application data rates and serial lane usage display screen visible blanking display pixel clock frequency serial data rate per lane resolution pixel count overhead refresh [mhz] 1-chm 2-chm 3-chm rate 176x220 (qcif+) 38,720 20% 90 hz 4.2 mhz 125 mbps 240x320 (qvga) 76,800 20% 60 hz 5.5 mhz 166 mbps 640x200 128,000 20% 60 hz 9.2 mhz 276 mbps 138 mbps 352x416 (cif+) 146,432 20% 60 hz 10.5 mhz 316 mbps 158 mbps 352x440 154,880 20% 60 hz 11.2 mhz 335 mbps 167 mbps 320x480 (hvga) 153,600 20% 60 hz 11.1 mhz 332 mbps 166 mbps 800x250 200,000 20% 60 hz 14.4 mhz 432 mbps 216 mbps 640x320 204,800 20% 60 hz 14.7 mhz 442 mbps 221 mbps 640x480 (vga) 307,200 20% 60 hz 22.1 mhz 332 mbps 221 mbps 1024x320 327,680 20% 60 hz 23.6 mhz 354 mbps 236 mbps 854x480 (wvga) 409,920 20% 60 hz 29.5 mhz 443 mbps 295 mbps 800x600 (svga) 480,000 20% 60 hz 34.6 mhz 346 mbps 1024x768 (xga) 786,432 20% 60 hz 56.6 mhz 566 mbps 34 submit documentation feedback www.ti.com sclk 5.5mhz 18+3 pclk r[ 5: 0] g[ 5: 0] b[ 5: 0] hs, vs, de d[ 5: 0] d[ 11 : 6] d[ 17 : 12 ] hs, vs, de pixel clk vddx gnd 2x0.01uf 2x0.1uf vddx gnd 2x0.01uf 2x0.1uf rxen d0+ d0- clk+ clk- d0+ d0- clk+ clk- gnd 1. 8v 2. 7v gnd 1. 8v 2. 7v gnd gnd lcd wit h qvga resolut ion 21 r[ 5: 0] g[ 5: 0] b[ 5: 0] hs, vs, de sclk application processor (e.g. omap ) sn 65lvds 301 sn65lvds 302 display driver 2 fpc 5.5mhz 330mbps sin lcd with qvga resolution display driver 1 1.8v ls0 ls1 txen 1.8v ls0 ls1 si n sout sel2 sel1 sout en sclk sout ensin pclk pclk pclk
calculation example: hvga display SN65LVDS302 slls733b ? june 2006 ? revised february 2007 the following calculation shows an example for a half-vga display with the following parameters: display resolution: 480 x 320 frame refresh rate: 58.4 hz horizontal visible pixel: 480 columns horizontal front porch: 20 columns horizontal sync: 5 columns horizontal back porch: 3 columns vertical visible pixel: 320 lines vertical front porch: 10 lines vertical sync: 5 lines vertical back porch: 3 lines figure 42. hvga display calculation of the total number of pixel and blanking overhead: visible area pixel count: 480 320 = 153600 pixel total frame pixel count: (480+20+5+3) (320+10+5+3) = 171704 pixel blanking overhead: (171704-153600) ? 153600 = 11.8 % the application requires the following serial-link parameters: pixel clk frequency: 171704 58.4 hz = 10.0 mhz serial data rate: 1-channel mode: 10.0 mhz 30 bit/channel = 300 mbps 2-channel mode: 10.0 mhz 15 bit/channel = 150 mbps 35 submit documentation feedback www.ti.com entire display visible area visible area = 480 columns vsync =5 vbp =3 visible area =320 lines vfp=10 hsync =5 hbp hfp=20
how to determine interconnect skew and jitter budget (1) example: (2) SN65LVDS302 slls733b ? june 2006 ? revised february 2007 designing a reliable data link requires examining the interconnect skew and jitter budget. the sum of all transmitter, pcb, connector, fpc, and receiver uncertainties must be smaller than the available serial bit time. the highest pixel clock frequency defines the available serial bit time. the transmitter timing uncertainty is defined by t ppos in the transmitter data sheet. for a bit-error-rate target of 10-12, the measurement duration for tppos is 3 1012. the SN65LVDS302 receiver can tolerate a maximum timing uncertainty defined by t rskm . the interconnect budget is calculated by: f pclk (max) = 23 mhz (vga display resolution, 60 hz) transmission mode: 2-chm; t ppos (sn65lvds301) = 330 ps target bit error rate: 10 -12 t rskm (SN65LVDS302) = 1/(2*15*f pclk ) ? 480 ps = 969 ps the interconnect budget for cable skew & isi needs to be smaller than: figure 43. jitter budget 36 submit documentation feedback www.ti.com ppos rskm erconnect int t t t - = ps 639 t t t ppos rskm erconnect int = - = rskm d0, d1, d2rx internal sampling clock data period /2 ideal receiver strobe position ideal t pposn data transition r sposn : receiver input strobe position (min and max) r sposn (max) - r sposn (min) = skew rx + s&h rx + tj (rxpll(non-trackable) skew rx : receiver input skew (skew between clk and dx input) s&h rx : receiver input latch sample & hold uncertainty tj (rxpll(non-trackable) : intrinsic rx pll jitter above rx pll bandwidth; pll tj > f(bw rx ); tj=rj[ps-rms]*14 + dj[ps] tppos: transmitter output pulse position (min and max) t pposx (max) -t pposx (min) = tj txpll(non-trackable) + t txskew + t txdj tj txpll(non-trackable) : non-trackable tx pll jitter; this jitter is the integration of total jitter above the receiver pll bandwidth ; tj txpll > f (bwrx); tj=rj[ps-rms]*14 + dj[ps] t txskew : transmitter output skew (skew between clk and data) t txidj transmitter deterministic jitter of tx output stage (includes tx intersymbol interference isi) t pposn (max) t pposn (min) rskm: receiver skew marginrskm = skew pcb + xtalk pcb + isi pcb skew pcb : pcb induced skew (trace + connector); xtalk pcb : pcb induced cross-talk; isi pcb : inter-symbol interference of pcb; is dependent on interconnect frequency loss; may bezero for short interconnects. r sposn (max) r sposn (min) rskm
f/s-pin setting and connecting the SN65LVDS302 to an lcd driver SN65LVDS302 slls733b ? june 2006 ? revised february 2007 note: receiver pll tracking: to maximize the design margin for the interconnect, good rx pll tracking of the tx pll is important. flatlink3g requires the rx pll to have a bandwidth higher than the bandwidth of the tx pll. the SN65LVDS302 pll design is optimized to track the sn65lvds0301 pll particularly well, thus providing a very large receiver skew margin. a flatlink3g-compliant link must provide at least 225 ppm of receiver skew margin for the interconnect. it is important to understand the tradeoff between power consumption, emi, and maximum speed when selecting the f/s signal. it is beneficial to choose the slowest rise time possible to minimize emi and power consumption. unfortunately a slower rise time also reduces the timing margin left for the lcd driver. hence it is necessary to calculate the timing margin to select the correct f/s pin setting. the output rise time depends on the output driver strength and the output load. an lcd driver typical capacitive load is assumed with ~10pf. the higher the capacitive load, the slower will be the rise time. rise time of the SN65LVDS302 is measured as the time duration it takes the output voltage to rise from 20% of v dd and 80% of v dd and fall time is defined as the time for the output voltage to transition from 80% of v dd down to 20%. within one mode of operation and one f/s pin setting, the rise time of the output stage is fixed and does not adjust to the pixel frequency. due to the short bit time at very fast pixel clock speeds and the real capacitive load of the display driver, the output amplitude might not reach v dd and gnd saturation fully. to ensure sufficient signal swing and verify the design margin, it becomes necessary to determine that the output amplitude under any circumstance reaches the display driver?s input stage logic threshold (usually 30% and 70% of v dd ). figure 44 shows a worst-case rise time simulation assuming a lcd driver load of 16pf at vga display resolution. pclk is the fastest switching output. with f/s set to gnd (figure 44 -a), the pclk output voltage amplitude is significantly reduced. the voltage amplitude of the output data rgb[7:0], vs, hs, and de shows less amplitude attenuation because these outputs carry random data pattern and toggle equal or less than half of the pclk frequency. it is necessary to determine the timing margin between the lvds302 output and lcd driver input. figure 44. output amplitude as a function of output toggling frequency, capacitive load and f/s setting 37 submit documentation feedback www.ti.com rx rise/fall time 0.0v 0.2v 0.4v 0.6v 0.8v 1.0v 1.2v 1.4v 1.6v 1.8v 2.0v 100ns 150ns 200ns 250ns 300ns 350ns 400ns 450ns 500ns 550ns 600ns vod clk 22 mhz, f/s=1, cl=16 pf data 22 mbps, f/s=1, cl=16 pf application: vga (2-channel mode); f/s set to vdd ; display driver load ~16 pf ( (a) rx rise/fall time 0.0v 0.2v 0.4v 0.6v 0.8v 1.0v 1.2v 1.4v 1.6v 1.8v 2.0v 100ns 150ns 200ns 250ns 300ns 350ns 400ns 450ns 500ns 550ns 600ns vod clk 22 mhz, f/s=0, cl=16 pf data 22 mbps, f/s=0, cl=16 pf the data signal has a slower maximum switching frequency, and therefore drives a larger amplitude than the clock signal application: vga (2-channel mode); f/s set to gnd ; display driver load ~16 pf (b)
how to determine the lcd driver timing margin (3) example: SN65LVDS302 slls733b ? june 2006 ? revised february 2007 to determine the timing margin, it is necessary to specify the frequency of operation, identify the set-up and hold time of the lcd driver, and specify the output load of the SN65LVDS302 as a combination of the lcd driver input parasitics plus any capacitance caused by the connecting pcb trace. furthermore, the setting of pin f/s and the SN65LVDS302 output skew impact the margin. the total remaining design margin calculates as following: where: t dm ? design margin f pclk ? pixel clock frequency t dutp(max_error) ? maximum duty cycle error t rise(max) ? maximum rise or fall time; see t r/f under switching characteristics c l ? parasitic capacitance (sum of lcd driver input parasitics + connecting pcb trace) t skew ? clock to data output skew SN65LVDS302 at a pixel clock frequeny of 5.5mhz (qvga), and an assumed lcd driver load of 15 pf, the remaining timing margin is: as long as the set-up and hold time of the lcd driver are each less than 57 ns, the timing budget is met sufficiently. 38 submit documentation feedback www.ti.com t dm 1 2 ? pclk t dutp(max_error) t rise(max) c load 10 pf t osk t dutp(max_error) t dutp (max) 50 100% t pclk 5% 100% 1 5.5mhz 9.1ns t dm 1 2 5.5mhz 9ns 16ns (f s gnd) 15pf 10pf 500ps 57.3ns
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) SN65LVDS302zqe active bga mi crosta r juni or zqe 80 360 green (rohs & no sb/br) snagcu level-3-260c-168 hr SN65LVDS302zqer active bga mi crosta r juni or zqe 80 2500 green (rohs & no sb/br) snagcu level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 16-feb-2007 addendum-page 1

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or "enhanced plastic." only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security rfid www.ti-rfid.com telephony www.ti.com/telephony low power www.ti.com/lpw video & imaging www.ti.com/video wireless wireless www.ti.com/wireless mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2007, texas instruments incorporated

▲Up To Search▲

Price & Availability of SN65LVDS302

	To Download SN65LVDS302 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .